wip: IPC and Runtime
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@@ -2,6 +2,7 @@
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// Copyright (c) 2026 0xKSor
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#pragma once
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#include "Arch/Exceptions.h"
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#include <Types.h>
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static inline void CPUYield() {
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@@ -63,7 +64,7 @@ static inline void CPUEnableMMU(Address l0PhysicalAddress) {
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// MAIR_EL1 (Memory Attribute Indirection Register)
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// kPTENormalMem is index 0 and kPTEDeviceMem is index 1
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// 0xFF = Normal, 0x00 = Device
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UInt64 mair = (0xFFULL << 0) | (0x00ULL << 8);
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UInt64 mair = (0xFFULL << 0) | (0x00ULL << 8);
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// TCR_EL1 (Translation Control Register)
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// configures the mmu for 4kb pages and 48bit virtual addresses
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@@ -82,11 +83,11 @@ static inline void CPUEnableMMU(Address l0PhysicalAddress) {
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"msr tcr_el1, %1\n"
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"msr ttbr0_el1, %2\n" // set userspace root
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"msr ttbr1_el1, %2\n" // set kernelspace root
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"tlbi vmalle1is\n"
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"tlbi vmalle1is\n"
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"isb\n" // Instruction Synchronization Barrier
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:: "r"(mair), "r"(tcr), "r"(l0PhysicalAddress) : "memory"
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);
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// turn on the MMU in SCTLR_EL1 (System Control Register)
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// Bit 0 = M (MMU Enable), Bit 2 = C (Data Cache Enable), Bit 12 = I (Instruction Cache Enable)
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UInt64 sctlr;
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@@ -111,4 +112,13 @@ static inline void CPUSwitchAddressSpace(Address l0Physical) {
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);
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}
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#define CPUException(number) __asm__ volatile ("svc %0" :: "i" (number) : "memory")
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static inline void CPUCopyIPCRegisters(ExceptionsContext* source, ExceptionsContext* destination) {
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destination->x2 = source->x2;
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destination->x3 = source->x3;
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destination->x4 = source->x4;
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destination->x5 = source->x5;
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destination->x6 = source->x6;
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destination->x7 = source->x7;
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}
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#define CPUException(number) __asm__ volatile ("svc %0" :: "i" (number) : "memory")
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@@ -14,4 +14,4 @@ static inline UInt32 IOAddressRead32(Address address) {
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UInt32 value = *(volatile UInt32*)address;
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__asm__ volatile ("dsb ld" ::: "memory"); // wait till my read is finished physically
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return value;
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}
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}
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@@ -0,0 +1,7 @@
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#pragma once
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#include "Arch/Exceptions.h"
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#include <Types.h>
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#include <OS/Scheduler.h>
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UInt64 IPCSend(OSTask* sender, UInt64 handleID, UInt64 data);
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void IPCReceive(ExceptionsContext* receiverFrame);
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@@ -1,5 +1,6 @@
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#pragma once
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#include <Types.h>
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#include "../Common/bootinfo.h"
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#include <OS/Scheduler.h>
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void ModuleLoad(BootModule* module);
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OSTask* ModuleLoad(BootModule* module);
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@@ -4,12 +4,31 @@
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#pragma once
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#include <Types.h>
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typedef enum {
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kOSHandleTypeNone = 0,
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kOSHandleTypeTask
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} OSHandleType;
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typedef struct {
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OSHandleType type;
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Pointer object;
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} OSHandle;
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enum {
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kOSSchedulerTaskStackSize = 16 * 1024,
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kOSSchedulerExceptionNumber = 0xF0F0,
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kOSMaxHandlesPerProcess = 256,
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};
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typedef enum OSTaskState {
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OSTaskStateDead,
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OSTaskStateRunning,
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OSTaskStateReady,
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OSTaskStateBlocked,
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OSTaskStateSleeping,
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OSTaskStateBlockedReceive,
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OSTaskStateBlockedSend,
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} OSTaskState;
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typedef struct OSProcess {
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@@ -20,11 +39,12 @@ typedef struct OSProcess {
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Address heapCurrent;
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struct OSProcess* parent;
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ASCII name[32];
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OSHandle handles[kOSMaxHandlesPerProcess];
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} OSProcess;
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typedef struct OSTask {
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Address stackPointer;
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struct OSTask* next;
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UInt32 id;
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UInt32 sleepTicks;
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OSTaskState state;
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@@ -32,12 +52,10 @@ typedef struct OSTask {
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Pointer kernelStackBase;
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OSProcess* process;
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Int32 waitingForProcessId;
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} OSTask;
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enum {
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kOSSchedulerTaskStackSize = 16 * 1024,
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kOSSchedulerExceptionNumber = 0xF0F0
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};
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struct OSTask* next;
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struct OSTask* senderWaiting;
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} OSTask;
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extern UInt32 gOSSchedulerNextProcessID;
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@@ -46,3 +64,7 @@ OSTask* SchedulerSpawn(void(*entryPoint)(), OSProcess* owner, Boolean isUser, Ad
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Address SchedulerNext(Address stackPointer);
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void SchedulerYield(UInt64 ticks);
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UInt64 SchedulerGetNextProcessID();
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void SchedulerBlockCurrentTask(UInt32 newState);
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OSTask* SchedulerGetCurrentTask();
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Int32 SchedulerProcessAllocateHandle(OSProcess* process, OSHandleType type, Pointer object);
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Pointer SchedulerProcessGetHandle(OSProcess* process, UInt32 handleId, OSHandleType expectedType);
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@@ -0,0 +1,10 @@
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#pragma once
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#include <Types.h>
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#include <Arch/Exceptions.h>
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enum Syscalls {
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kSyscallSend,
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kSyscallReceive,
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};
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Address SyscallDispatch(ExceptionsContext* frame);
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