feat(scheduler): working scheduler

Kernel/Include/Arch/CPU.h

@@ -73,3 +73,16 @@ static inline void CPUEnableMMU(Address l0PhysicalAddress) {
         : "=r"(sctlr) : "r"(sctlr_flags) : "memory"
     );
 }
+
+static inline void CPUSwitchAddressSpace(Address l0Physical) {
+    __asm__ volatile(
+        "dsb ishst\n"             // wait till all previous writes are finished physically
+        "msr ttbr0_el1, %0\n"     // Update TTBR0_EL1 (userspace)
+        "tlbi vmalle1is\n"        // Reset TLB cache
+        "dsb ish\n"               // wait for tlb cache to reset
+        "isb\n"                   // Clear instruction pipeline
+        :: "r" (l0Physical) : "memory"
+    );
+}
+
+#define CPUException(number) __asm__ volatile ("svc %0" :: "i" (number) : "memory")

Kernel/Include/Arch/Exceptions.h

@@ -36,6 +36,8 @@ typedef struct ExceptionsContext {
     UInt64 elr_el1; // pc
     UInt64 spsr_el1; // cpu status
     UInt64 esr_el1; // error reason
+    UInt64 sp_el0; // user's stack
+    UInt64 padding; // align to 16 bytes
 } ExceptionsContext;
 
 typedef enum ExceptionsType {

Kernel/Include/Arch/GIC.h

@@ -25,4 +25,4 @@ enum {
 
 void GICInitialize(Pointer gicdVirtBase, Pointer giccVirtBase);
 void GICEnableInterrupt(UInt32 irqID);
-void GICDispatch(ExceptionsType type);
+Address GICDispatch(ExceptionsContext* frame, ExceptionsType type);

Kernel/Include/Arch/Timer.h

@@ -1,8 +1,11 @@
 #pragma once 
 #include <Types.h>
+#include <Arch/Exceptions.h>
 
 static const UInt64 kTimerFrequency = 1000; // 1ms
 static const UInt8 kTimerIRQ = 27;
 
 void TimerInitialize();
-void TimerReset(UInt64 interval);
+void TimerReset(UInt64 interval);   
+Address TimerHandler(ExceptionsContext* frame);
+UInt64 TimerGetCounter();