feat(scheduler): working scheduler

Kernel/Include/Arch/CPU.h

@@ -73,3 +73,16 @@ static inline void CPUEnableMMU(Address l0PhysicalAddress) {
         : "=r"(sctlr) : "r"(sctlr_flags) : "memory"
     );
 }
+
+static inline void CPUSwitchAddressSpace(Address l0Physical) {
+    __asm__ volatile(
+        "dsb ishst\n"             // wait till all previous writes are finished physically
+        "msr ttbr0_el1, %0\n"     // Update TTBR0_EL1 (userspace)
+        "tlbi vmalle1is\n"        // Reset TLB cache
+        "dsb ish\n"               // wait for tlb cache to reset
+        "isb\n"                   // Clear instruction pipeline
+        :: "r" (l0Physical) : "memory"
+    );
+}
+
+#define CPUException(number) __asm__ volatile ("svc %0" :: "i" (number) : "memory")