// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright (c) 2026 0xKSor

.macro ventry type
    .align 7
    sub sp, sp, #288 // save 288 bytes of stack
    stp x0, x1, [sp, #0] // move stack
    mov x1, #\type // move type to x1
    b ExceptionsTrapEntry
.endm

.section .text.vectors
.align 11
.global vectors
ExceptionsVectorsTable:
    // EL1t (curr EL with SP0)
    ventry 0 // Sync
    ventry 1 // IRQ
    ventry 2 // FIQ
    ventry 3 // SError

    // EL1h (curr EL with SP1)
    ventry 4 // Sync
    ventry 5 // IRQ
    ventry 6 // FIQ
    ventry 7 // SError

    // EL0 (lower EL 64-bit from userspace)
    ventry 8 // Sync
    ventry 9 // IRQ
    ventry 10 // FIQ
    ventry 11 // SError

    // EL0 (lower EL 32-bit from userspace)
    ventry 12; ventry 13; ventry 14; ventry 15

ExceptionsTrapEntry:
    stp x2, x3, [sp, #16 * 1]
    stp x4, x5, [sp, #16 * 2]
    stp x6, x7, [sp, #16 * 3]
    stp x8, x9, [sp, #16 * 4]
    stp x10, x11, [sp, #16 * 5]
    stp x12, x13, [sp, #16 * 6]
    stp x14, x15, [sp, #16 * 7]
    stp x16, x17, [sp, #16 * 8]
    stp x18, x19, [sp, #16 * 9]
    stp x20, x21, [sp, #16 * 10]
    stp x22, x23, [sp, #16 * 11]
    stp x24, x25, [sp, #16 * 12]
    stp x26, x27, [sp, #16 * 13]
    stp x28, x29, [sp, #16 * 14]

    mrs x21, elr_el1
    mrs x22, spsr_el1
    mrs x23, esr_el1
    mrs x24, sp_el0

    stp x30, x21, [sp, #16 * 15]
    stp x22, x23, [sp, #16 * 16]
    stp x24, xzr, [sp, #16 * 17]

    mov x0, sp
    bl ExceptionsHandler
    mov sp, x0

    ldp x24, xzr, [sp, #16 * 17]
    msr sp_el0, x24

    ldp x22, x23, [sp, #16 * 16]
    msr spsr_el1, x22

    ldp x30, x21, [sp, #16 * 15]
    msr elr_el1, x21

    ldp x28, x29, [sp, #16 * 14]
    ldp x26, x27, [sp, #16 * 13]
    ldp x24, x25, [sp, #16 * 12]
    ldp x22, x23, [sp, #16 * 11]
    ldp x20, x21, [sp, #16 * 10]
    ldp x18, x19, [sp, #16 * 9]
    ldp x16, x17, [sp, #16 * 8]
    ldp x14, x15, [sp, #16 * 7]
    ldp x12, x13, [sp, #16 * 6]
    ldp x10, x11, [sp, #16 * 5]
    ldp x8, x9, [sp, #16 * 4]
    ldp x6, x7, [sp, #16 * 3]
    ldp x4, x5, [sp, #16 * 2]
    ldp x2, x3, [sp, #16 * 1]
    ldp x0, x1, [sp, #0]

    add sp, sp, #288
    eret

.global ExceptionsVectorsInit
ExceptionsVectorsInit:
    adr x0, ExceptionsVectorsTable
    msr vbar_el1, x0
    isb
    ret