karina
114 lines
3.8 KiB
C
114 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-3.0-or-later
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// Copyright (c) 2026 0xKSor
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#pragma once
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#include <Types.h>
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static inline void CPUYield() {
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__asm__ volatile ("yield" ::: "memory");
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}
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static inline void CPUWaitForInterrupt() {
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__asm__ volatile ("wfi" ::: "memory");
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}
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static inline void CPUDisableInterrupts() {
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__asm__ volatile ("msr daifset, #3" ::: "memory");
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}
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static inline void CPUEnableInterrupts() {
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__asm__ volatile ("msr daifclr, #3" ::: "memory");
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}
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static inline UInt64 CPUGetFAR() {
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UInt64 far;
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__asm__ volatile ("mrs %0, far_el1" : "=r" (far));
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return far;
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}
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static inline void CPUInvalidateTLB(Address virt) {
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__asm__ volatile(
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"dsb ishst\n"
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"tlbi vaae1is, %0\n"
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"dsb ish\n"
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"isb\n"
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:: "r" (virt >> 12) : "memory"
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);
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}
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static inline void CPUCleanAndInvalidateCode(Pointer codeVirt, Size size) {
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// Read cache line sizes from CTR_EL0
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UInt64 ctr;
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__asm__ volatile ("mrs %0, ctr_el0" : "=r" (ctr));
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UInt64 dcacheLineSize = 4ULL << ((ctr >> 16) & 0xF);
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UInt64 icacheLineSize = 4ULL << (ctr & 0xF);
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Address addr = (Address)codeVirt;
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Address end = addr + size;
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// Clean D-cache to PoU (Point of Unification)
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for (Address va = addr; va < end; va += dcacheLineSize) {
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__asm__ volatile ("dc cvau, %0" :: "r" (va) : "memory");
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}
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__asm__ volatile ("dsb ish" ::: "memory");
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// Invalidate I-cache to PoU
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for (Address va = addr; va < end; va += icacheLineSize) {
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__asm__ volatile ("ic ivau, %0" :: "r" (va) : "memory");
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}
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__asm__ volatile ("dsb ish\nisb" ::: "memory");
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}
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static inline void CPUEnableMMU(Address l0PhysicalAddress) {
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// MAIR_EL1 (Memory Attribute Indirection Register)
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// kPTENormalMem is index 0 and kPTEDeviceMem is index 1
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// 0xFF = Normal, 0x00 = Device
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UInt64 mair = (0xFFULL << 0) | (0x00ULL << 8);
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// TCR_EL1 (Translation Control Register)
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// configures the mmu for 4kb pages and 48bit virtual addresses
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// t0sz/t1sz = 16 (64-48 = 16)
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// tg0/tg1 = 4kb granule
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UInt64 tcr = (16ULL << 0) | // T0SZ (userspace size)
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(16ULL << 16) | // T1SZ (kernelspace size)
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(0ULL << 14) | // TG0 (User 4KB)
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(2ULL << 30) | // TG1 (Kernel 4KB)
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(3ULL << 28) | // SH1 (Inner Shareable)
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(3ULL << 12) | // SH0 (Inner Shareable)
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(5ULL << 32); // IPS
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__asm__ volatile (
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"msr mair_el1, %0\n"
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"msr tcr_el1, %1\n"
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"msr ttbr0_el1, %2\n" // set userspace root
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"msr ttbr1_el1, %2\n" // set kernelspace root
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"tlbi vmalle1is\n"
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"isb\n" // Instruction Synchronization Barrier
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:: "r"(mair), "r"(tcr), "r"(l0PhysicalAddress) : "memory"
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);
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// turn on the MMU in SCTLR_EL1 (System Control Register)
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// Bit 0 = M (MMU Enable), Bit 2 = C (Data Cache Enable), Bit 12 = I (Instruction Cache Enable)
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UInt64 sctlr;
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UInt64 sctlr_flags = 0x1005; // set bits 0 (M), 2 (C), and 12 (I)
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__asm__ volatile (
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"mrs %0, sctlr_el1\n"
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"orr %0, %0, %1\n"
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"msr sctlr_el1, %0\n"
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"isb\n"
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: "=r"(sctlr) : "r"(sctlr_flags) : "memory"
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);
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}
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static inline void CPUSwitchAddressSpace(Address l0Physical) {
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__asm__ volatile(
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"dsb ishst\n" // wait till all previous writes are finished physically
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"msr ttbr0_el1, %0\n" // Update TTBR0_EL1 (userspace)
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"tlbi vmalle1is\n" // Reset TLB cache
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"dsb ish\n" // wait for tlb cache to reset
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"isb\n" // Clear instruction pipeline
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:: "r" (l0Physical) : "memory"
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);
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}
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#define CPUException(number) __asm__ volatile ("svc %0" :: "i" (number) : "memory") |