karina
68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
#include <Arch/GIC.h>
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#include <Arch/Exceptions.h>
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#include <Arch/Timer.h>
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#include <OS/Log.h>
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static volatile UInt32* GICD = nullptr;
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static volatile UInt32* GICC = nullptr;
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void GICInitialize(Pointer gicdVirtBase, Pointer giccVirtBase) {
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GICD = (volatile UInt32*)gicdVirtBase;
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GICC = (volatile UInt32*)giccVirtBase;
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GICD[kGICDCTLR / 4] = 0; // disable Distributor (gicd)
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UInt32 typer = GICD[kGICDTYPER / 4]; // how many interrupts are supported
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UInt32 maxIRQS = 32 * ((typer & 0x1F) + 1); // total number of interrupts
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OSLog("GIC: maxIRQS: %d\n", maxIRQS);
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for (UInt32 i = 0; i < maxIRQS / 32; i++) {
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GICD[kGICDICENABLER / 4 + i] = 0xFFFFFFFF; // clear enable
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GICD[kGICDICPENDR / 4 + i] = 0xFFFFFFFF; // clear pending
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}
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for (UInt32 i = 0; i < maxIRQS / 4; i++) {
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GICD[kGICDIPRIORITYR / 4 + i] = 0xA0A0A0A0; // set priority 0xA0 for all interrupts
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}
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for (UInt32 i = 8; i < maxIRQS / 4; i++) {
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GICD[kGICDITARGETSR / 4 + i] = 0x01010101; // set interrupts id >= 32 for CPU 0
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}
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GICD[kGICDCTLR / 4] = 1; // enable Distributor (gicd)
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GICC[kGICCCTLR / 4] = 0; // disable cpu interface
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GICC[kGICCPMR / 4] = 0xFF; // set lowest priority (accept all interrupts)
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GICC[kGICCCTLR / 4] = 1; // enable CPU interface (gicc)
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OSLog("GICv2 initialized.\n");
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}
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void GICEnableInterrupt(UInt32 irqID) {
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UInt32 regOffset = irqID / 32;
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UInt32 bitMask = 1 << (irqID % 32);
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GICD[kGICDISENABLER / 4 + regOffset] = bitMask;
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}
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UInt32 GICCReadIAR(void) {
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return GICC[kGICCIAR / 4];
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}
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void GICCWriteEOIR(UInt32 irqID) {
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GICC[kGICCEOIR / 4] = irqID;
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}
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void GICDispatch(ExceptionsType type) {
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OSLog("GICDispatch: %d\n", type);
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if (type != ExceptionsIRQEl1h && type != ExceptionsIRQEl064) return;
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UInt32 irqID = GICCReadIAR() & 0x3FF;
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if (irqID == 1023) return; // spurious interrupt
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if (irqID == kTimerIRQ) {
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OSLog("Timer IRQ\n");
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TimerReset(kTimerFrequency);
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}
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GICCWriteEOIR(irqID);
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}
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